In recent years, miniaturization, thinning and high performance of electronic devices represented by mobile phones, smart phones, tablet terminals, etc., have been required, and semiconductor apparatus constituting the electronic devices have also been required to be miniaturized, thinned and high density packaging. As a semiconductor package manufacturing technology realizing such a requirement, a fan-out wafer level package technology attracts a great deal of attention. The fan-out wafer level package is a general term for packages that form rewiring layers also outside the area of semiconductor devices by using the conventional wafer level rewiring technology. In a BGA (Ball Grid Array) type package, etc., as a general type of semiconductor package, it is necessary to mount a semiconductor device on a package substrate and perform wire bonding. On the other hand, in the fan-out wafer level package, a small package of a bare chip level can be realized by replacing the package substrate, the wiring, etc., with thin film wiring bodies and bonding them to the semiconductor device.
As a method for manufacturing such a fan-out wafer level package, it has been known a method in which a plurality of semiconductor devices are temporarily fixed on a support substrate to which a double-sided adhesive sheet is adhered as a temporary fixing material, after a plurality of the semiconductor devices are collectively encapsulated with an encapsulating resin, the adhesive sheet is removed from the encapsulated body, and then a rewiring layer is formed on the surface of the encapsulated body to which the adhesive sheet has been adhered (see Patent Documents 1 to 3). In these methods for manufacturing a fan-out wafer level package, a large area is collectively encapsulated from the viewpoint of a manufacturing cost, but warpage of the package, in particular, warpage after removal of the support substrate and the temporary fixing material is a serious problem.